Semiconductor devices mounted on an electronic device substrate or the like are manufactured by cutting a semiconductor wafer into semiconductor chips each including individual semiconductor apparatuses as integrated circuits implemented in a wafer state. In recent years, semiconductor chips are decreasing in thickness, and therefore, becoming harder to handle. In line with this, it has been proposed to cut a semiconductor wafer into semiconductor chips by plasma etching, which is called plasma dicing.
Plasma dicing means to cut a semiconductor wafer along lattice-shaped scribe lines indicating cutting positions by plasma etching, while the wafer is masked with a resist film mask except for the scribe lines. Therefore, plasma dicing requires a process for forming a mask over the semiconductor wafer. Conventionally, such a mask is formed as follows: a scribe line pattern is transferred using a photosensitive material based on photolithography (Patent Literature 1), or a mask layer is formed on the surface of the semiconductor wafer and then the area of the mask layer that is on the scribe line region is removed by laser radiation (Patent Literature 2).
However, these conventional mask forming processes are costly. More specifically, the mask formation based on photolithography is high cost because photolithography is intended to be used for the formation of high precision patterns of integrated circuits or the like, thereby requiring complicated steps and expensive equipment. The mask formation by laser radiation is also high cost because it requires equipment for laser radiation. The cost for mask formation is a concern not only in plasma dicing, but also in various other processes for processing a substrate using plasma etching. Examples of such processes are as follows: a process for forming through-holes in a substrate, a process for processing a substrate for MEMS (micro electro mechanical systems) devices, and a process for forming integrated circuits on a display transparent panel.    Patent Literature 1: Japanese Patent Unexamined Publication No. 2004-172364    Patent Literature 2: Japanese Patent Unexamined Publication No. 2005-191039